As integrated circuit devices have become smaller, the importance of even very small defects in silicon wafers has grown accordingly. It is common practice to use single crystal silicon wafers to provide a medium which is as defect-free as possible for the manufacture of integrated circuit devices. It is widely appreciated, however, that although these silicon wafers are formed as a single crystal structure, they are not without defects. Examples of such defects are: loop dislocations, s-pits, and slip plane dislocations.
Loop dislocations and s-pit defects are disruptive of the silicon crystalline lattice structure, and can have serious adverse effects on integrated circuit devices, since disruption of the lattice structure destroys the semiconductor properties of the silicon material. For example, a diode junction transected by a loop dislocation is effectively rendered non-functional. These disruptive defects are large enough and disruptive enough to have significant impact on semiconductor devices with line widths (design rules) of greater than 0.5 .mu.m (microns, or millionths of a meter). Since 0.5 .mu.m geometries (line widths, or design rules) are now relatively commonplace, s-pits and loop dislocations have received a great deal of attention in the semiconductor design and manufacturing community, and have been effectively dealt with. (Clearly, the effect of loop dislocations and s-pits on smaller geometries would be similar, and dealt with in the same manner.) Slip plane dislocations (also known as slip dislocations), on the other hand, do not pose significant problems for device geometries of 0.5 .mu.m and above, and have been largely ignored in practice.
Slip dislocations ("slips") are caused by a sliding of crystal planes over one another in response to internal stresses (often process induced) within the crystalline material. These "slips" cause the planes to move anywhere from 100 .ANG. to 2000 .ANG. (Angstroms; an Angstrom is equal to one ten-thousandth of a micron) relative to one another (about 0.01 to 0.2 microns). A die which has experienced a slip dislocation is sometimes referred to as a "ripped" die, in analogous reference to terminology from carpentry where "ripping" refers to cutting through a board in substantial alignment with the grain of the wood.
Although slip dislocations cause physical shifts in the crystalline structure, they are not disruptive of the crystal lattice, that is, the semiconductor properties of the silicon material are unaffected by the physical shift of the crystal planes. A portion of the crystal lattice shifts during slip dislocation, but the lattice structure itself is not damaged. Therefore, a slip dislocation induced during semiconductor processing may be treated as a substantially "mechanical" (versus electrical) problem which becomes significant only when sufficient physical misalignment of a previously formed electrical structure occurs to cause it to misoperate.
For semiconductor devices fabricated to 0.5 micron (and above) line rules (geometry) slip dislocations are generally neglected since, unlike loop dislocation, there is no catastrophic lattice disruption, and the resultant mechanical misalignment of electrical devices formed to these line rules is small compared to the size of the devices. For smaller geometries, (e.g. 0.25 .mu.m and below), the presence of slip dislocations has a significant damaging effect. The essence of the damage by slip dislocations is not to spoil the electrical characteristics of the junction, as would be seen with the above mentioned loop dislocation, but rather to create physical displacements which are sufficiently large that individual devices are no longer in sufficiently accurate registration with each other to work as a circuit. Further, it should be recognized that a small device (0.25 .mu..mu.m design rules and below) which has been transected (e.g., bisected) by a slip dislocation (particularly larger slip dislocations, e.g., 0.1 microns or greater) may no longer function as designed, because its distorted shape may no longer adhere to the design rules for the device.
Since slip dislocations occur as a "sliding" of crystal planes over one another, the orientation of the crystal planes in a silicon wafer define and constrain the orientation of slip dislocations. The orientation of the crystal planes is determined by the orientation of the original crystal from which the wafer was derived. A typical orientation of silicon crystal for semiconductor device fabrication is the &lt;1-0-0&gt; crystal orientation. Silicon wafers sawn in this orientation have major crystal slip planes parallel to the X and Y axis of the wafer. Slip dislocations are expected and observed parallel to the X and Y direction of the wafer. Rectangular semiconductor dies are typically oriented on a silicon wafer such that potential slip dislocations can occur only perpendicular to the sides of the dies.
In the processing of semiconductor wafers by photolithography, it is necessary, at certain process steps, to align a photolithographic mask (or, more accurately, a projected image of the mask) with a semiconductor die site on a semiconductor wafer. The die is coated with a light-sensitive photoresist and is exposed to an image of the mask. The photoresist is then "developed" to leave behind a pattern of photoresist in the image of the mask. The wafer is then processed (i.e., by etching, diffusion, oxidation, etc.), with areas covered by the photoresist being substantially impervious to the process. It is, in part, by this method that circuit elements are formed in silicon wafers to create integrated circuit devices.
Before exposing the wafer to the image of the mask, which typically represents a single die, the image must be properly aligned with the die site to be exposed on the wafer. This is accomplished by means of one or more alignment targets formed in an earlier processing step at known locations on the wafer. The alignment targets identify the exact location of die sites on the wafer and provide a means for accurate alignment of different photolithographic masks in different processing steps. This mask alignment is usually accomplished by a mask alignment system, such as that described in commonly-owned U.S. Pat. No. 4,652,134, incorporated by reference herein. This patent describes techniques for improving alignment accuracy of mask alignment systems. Modern measurement and alignment systems are capable of measuring points on a die and aligning masks to within an accuracy of about 50 nm (nanometers, or billionths of a meter).
Often, modern mask alignment systems rely upon a plurality of alignment marks defining a die site, and use these marks to identify not only the location, but the rotational orientation of a semiconductor die site. Unfortunately, on semiconductor devices using design rules of 0.25 microns and less, slip plane dislocations can completely frustrate the operation of such alignment systems. A slip plane dislocation will cause these systems to incorrectly identify a small die rotation. The mask is then rotated to match the perceived die rotation, which causes secondary rotation-induced mask alignment errors unrelated to the slip dislocation. Worse still, the rotation does not improve the alignment of the mask to die features in the vicinity of the slip plane dislocation.